Power analysis and minimization techniques for embedded DSP software

Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded DSP processor based on physical current measurements. Signiicant points of diierence have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general-purpose commercial microprocessors 1, 2]. In particular, the eeect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual-memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above eeects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the eeectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been veriied through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modiication, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modiied programs either improve or remain unchanged.